This invention relates to an analog voltage measuring device, particularly for use in a non-volatile memory architecture.
Non-volatile memories, and especially flash memories, use a number of analog voltages for handling memory cell program and erase operations.
More particularly, it is known how to derive, from a reference voltage such as a bandgap voltage VBG, voltage references of elevated value to apply to the terminals of the memory cells. These elevated voltages include: a row decode reference VPCX and column decode reference VPCY for terminals of memory cells in the same row/column during a decoding step; and a program/erase voltage reference VPD for both the drain terminals of the selected cells during a writing step, and the source terminals of cells contained in a selected sector during an erasing step; a negative erase voltage reference HVNEG for the source terminals of cells contained in a decoded row during a negative gate voltage erasing step.
These elevated voltage references usually have different values according to the type of the modifying operation (program, erase, recover depleted cells) or verifying operation (program verify, erase verify, depletion verify) to be performed for the memory cells. Consequently, the operational structures which produce these voltage references need to be re-configurable, as well as stable and accurate, and able to provide reproducible outputs.
One example of a conventional operational structure adapted to generate a plurality of voltage references is shown at 1 in FIG. 1.
The operational structure 1 includes an operational amplifier 2 having a non-inverting input terminal T1 connected to a bandgap reference VBG, an enable input terminal T2 receiving an enable signal ENABLE, an inverting input terminal T3, and a supply terminal T4 connected to a high supply voltage reference HV.
The operational structure 1 also has an output terminal T5, outputting a high output voltage reference XREF. The high output voltage reference XREF is provided as a multiple of the bandgap reference VBG, through the operational amplifier 2.
The output terminal T5 is feedback connected to the inverting input terminal T3 via a resistive divider 3 and a passgate feedback network 4.
In particular, the resistive divider 3 includes first R1, second R2, third R3 and fourth R4 resistive elements connected together in series between the output terminal T5 of the operational amplifier 2 and a voltage reference, specifically a ground GND.
The passgate feedback network 4 includes first PG1, second PG2 and third PG3 passgates, which are connected between the inverting input T3 of the operational amplifier 2 and a first intermediate circuit node Y1 formed between the first and second resistive elements R1 and R2, a second intermediate circuit node Y2 formed between the second and third resistive elements R2 and R3, and a third intermediate circuit node Y3 formed between the third and fourth resistive elements R3 and R4, respectively.
The passgates PG1, PG2 and PG3 are driven by first X1, second X2 and third X3 control signals, respectively, as well as by their respective negated signals /X1, /X2 and /X3.
To provide re-configurability for the operational structure 1, the high output voltage reference XREF is made to vary with the values of the input voltages X1, X2 and X3, as illustrated schematically by the plots vs. time of FIG. 2.
In the test mode, the operational structure 1 is checked for proper operation by activating the control signals X1, X2, X3, the bandgap reference VBG, and the enable signal ENABLE, so that the state of the operational amplifier 2 can be reproduced at the output. After a time period which is dependent on a settling time of the output signal from the operational amplifier 1, it thus becomes necessary to access the value of the high output voltage reference XREF to verify the state of the operational amplifier.
Additionally to producing accurate references, the operational structure 1 is expected to provide reasonable settling times of the references, in order to make the overall duration of the modify/verify operations performed for the memory cells by the structure, the shortest possible.
Briefly, in the testing or debugging mode of a storage architecture which includes an operational structure 1 for generating a plurality of voltage references, it is of vital importance to check on the accuracy of the values and the settling time of all the high voltage references involved.
Conventional storage architectures allow for three different methods of performing the last-mentioned operation: using a test pad provided on the storage architecture chip for the application of microprobes; transferring the value of the high output voltage reference XREF outside of the operational structure 1 through an external terminal or pad already provided on the chip and serving some other function, such as handling a data or address input (user mode pad), in normal operation of the chip; and providing a pad separate from the above chip pads (dummy pad or test mode-only pad) for only handling access from the outside and measuring the high output voltage reference XREF.
These prior measuring methods imply, in particular, different layouts for the chip containing the storage architecture to be measured, as illustrated schematically in FIG. 3 by a memory chip 5 including an operational structure 1 to generate a high output voltage reference XREF on an output terminal T5, as previously described and shown in FIG. 1.
The memory chip 5 includes:
a test pad 6, which is connected directly to the output terminal T5 and, therefore, to the high output voltage reference XREF to be measured by the first of the aforementioned measuring methods;
a pad 7 of the user mode circuitry 8, which is already provided on the memory chip 5 and connected to the output terminal T5 via a de-coupling block 9 driven by a signal TEST to enter the test mode; and
a dedicated pad 10, which is added to the memory chip 5 and connected to the output terminal T5 through another de-coupling block 11 driven by the signal TEST to enter the test mode.
In particular, the de-coupling blocks 9 and 11 include respective MOS transistors, M1 and M2, having their source terminals connected to the output terminal T5, drain terminals connected to the pads 7 and 10, and gate terminals driven by the signal TEST through respective logic inverters INV1 and INV2.
The inverters INV1 and INV2 have control terminals connected to the drain terminals of the transistors M1 and M2, and thence to the output terminal T5.
The above methods of accessing and measuring the high voltage reference XREF inside the memory architecture, and the corresponding chip layouts, are quite simple but show important limitations, as specified herein below.
In a first method, the test pad 6 of the memory chip 5 is used.
To apply this measuring method, the memory chip 5 would have to be in an open package. The method cannot be used with the memory chip 5 mounted to a board. Furthermore, since micro-probes can only be used at room temperature, any measurements which rely on a temperature analysis are ruled out.
In a second method, the test pad 7 of the user circuitry 8 of the memory chip is used.
This measuring method can be applied also to memory chips 5 placed in sealed packages. The algorithm for entering the test mode, whereby the value of the high output voltage reference XREF to be measured is transferred to the pad 7, should not clash with the user mode circuitry 8, and must be implemented without making access to the other test modes of the memory chip 5 too complicated.
Specifically, the pad 7 for measuring XREF cannot be one of those to be selected for accessing the test modes of the memory chip 5. Were the pad 7 one for selection in other test modes, the associated test algorithms would have to provide for first forcing the value presented at the pad, and then reading the same. In this case, it would be impossible to utilize test algorithms which have been written for previous devices, and at any rate, once the high output voltage reference XREF is measured, another test algorithm could not be linked to the current one.
In addition, the method of testing XREF by means of a pad 7 of the user mode circuitry 8 may weaken the pad capability to withstand ESDs (ElectroStatic Discharges). In fact, for transferring the value of XREF outside the memory architecture, PMOS components, such as the transistor M1 of the de-coupling block 9, are added to the standard circuitry of pad 7 for communicating the pad to internal circuits of the memory chip 5, and these circuits may be susceptible to ESDs.
A typical example of a circuit connected to the pad 7 is the circuit for generating the bandgap reference VBG, which is usually made up of low-voltage components. In particular, should the gate terminal of the transistor M1 be floating toward ground, an EDS applied to the pad 7 could propagate to and damage the internal circuitry 8.
In the third method, the dedicated pad 10 of the memory chip 5 is used.
To use this measuring method, the package containing the memory chip 5 must be provided with more pins, in addition to those needed for normal operation (user mode) of the memory chip 5. This scheme is, therefore, a costly one.
Also, if the additional pin 10 is disconnected, the high output voltage reference XREF cannot be measured with the piece installed on a board.
This measuring method, and the additional pad 10 that goes with it, poses, moreover, the same ESD problems as previously discussed.
Finally, it will be appreciated that, as the number of voltage references to be measured increases, a larger number of measurement pads would have to be provided with any of the above-discussed measuring methods and chip layouts.
Until now, no method and circuit was available to determine, outside of the memory chip, instantaneous information about the level and settling time of the increased voltage references, using existing circuit structures within the memory chip.
Provided in embodiments of the invention is a method to measure an analog voltage value in a memory device. The method involves selecting one out of many analog voltage values that are generated inside the memory device and transferring the selected analog value onto a communication line. From the communication line, the selected analog value is converted into a digital value and then the digital value is sent to the output pads of the memory chip.
Another embodiment of the invention includes a memory circuit containing a device for measuring analog voltages. One of the available voltages is selected and passed through a multiplexer to a facility line. An analog to digital converter accepts the voltage from the facility line and converts it into a digital signal and passes it to a set of memory output pads.
In one specific embodiment, the analog to digital converter is a counter-ramp converter which includes a hysteresis type of comparator. In some embodiments, a n-bit counter is used, which is already present in prior art memory devices.
In yet a further embodiment, the measuring device contains a small memory device that has been programmed with expected or anticipated analog voltage values. Thereafter, checking the voltage requires only the checking to see if the actual value of the voltage to be read is within a given range around the stored voltage value.
The invention relates, particularly but not exclusively, to a measuring device for non-volatile flash memory architectures, and the description which follows will cover this field of application for convenience of explanation only.